Senior Embedded Software Engineer (C++) - Hardware Safety
Latitude · Pittsburgh, PA, Palo Alto, CA, Detroit, MI, Remote
About this role
## Latitude AI — Senior Embedded Software Engineer (C++) | Hardware Safety Latitude AI (lat.ai) develops automated driving technologies, including L3, for Ford vehicles at scale—making travel safer, less stressful, and more enjoyable. ### Meet the team The Embedded Software team builds foundational platform software across the company. The **Hardware Safety & Power Systems** group specializes in **real-time firmware** that orchestrates safe system behavior during **fault conditions, power transitions, and thermal events**. ### What you’ll do - **Own end-to-end architecture** of hardware safety and power management systems (safe-state strategies, power sequencing across cores/PMICs, thermal throttling, watchdog orchestration) with **ASIL-B/C** safety goals. - **Implement low-level drivers and firmware** for safety-critical ICs (PMIC, voltage supervisor, thermal monitor) using datasheets and the **TDA4 Functional Safety Manual**; run on **bare metal and FreeRTOS**. - **Lead hardware-software safety diagnostic frameworks** by integrating TI Safety Diagnostic Library components (LBIST, PBIST, ECC, DCC, ESM) and ensuring diagnostic coverage maps to **ISO 26262** hardware fault metrics. - **Perform deep-dive code reviews** to keep PRs simple, bug-free, and aligned with a unified architectural vision (clean driver interfaces, consistent error handling, testable patterns). - **Serve as the SME** for hardware-firmware-safety interfaces; navigate ambiguity and influence decisions with evidence-based safety constraints. - **Mentor engineers** on embedded safety patterns (code review discipline, driver architecture, RTOS integration, ISO 26262 traceability, functional safety reasoning). ### What you’ll need to succeed - **Bachelor’s** in a relevant field + **4+ years** experience (or **Master’s + 2+**, or **PhD**). - **Embedded C/C++** experience with strong understanding of embedded constraints (no exceptions/RTTI, careful memory management) and testable abstractions. - **ARM-based SoC expertise**, especially **ARM Cortex-R5F** (MMIO, interrupt controllers/VIM, MPU config, cache behavior, memory barriers) and register-level debugging. - Experience configuring **MPUs and hardware firewalls** for spatial/temporal isolation in multi-core safety-critical environments. - Ability to build/refactor **HALs** for multiple targets/RTOS environments/variants. - Strong **root-cause** skills for complex system failures (power sequencing hangs, watchdog feed misses, thermal throttle races, interrupt latency issues). - Ability to spot pitfalls in low-level designs (power rail ordering, watchdog timeout config, voltage threshold hysteresis) and express designs clearly (state diagrams, timing requirements, register sequences). - Expert use of embedded debugging tools (e.g., **JTAG**, on-target debugging, logic analyzers). - Deep understanding of **RTOS** (FreeRTOS and/or SafeRTOS): task lifecycle, sync, interrupt handling, timing constraints, preemption/priority inversion/stack requirements. - Direct experience developing **drivers for safety-critical ICs** (SPI/I2C, register configuration, fault handling, diagnostic integration). - Foundational knowledge of **ISO 26262 ASIL-B/C** concepts (safe-state strategies, diagnostic coverage, fault tolerance allocation, traceability). ### Nice to have - Experience with **TDA4 / J784S4 (Jacinto 7)** and TI tooling (PSDK, SDL), register maps, peripheral architecture. - Linux embedded development (gtests, Python, **Bazel
Listing freshness
CronJobs last confirmed this listing 23h ago. If its source stops confirming the opening for seven days, this page is removed from active inventory.