Sr. Physical Design Flow & Methodology Engineer
Lightmatter · Boston, MA
About this role
**Lightmatter — Sr. Physical Design Flow & Methodology Engineer** Lightmatter is leading the revolution in AI data center infrastructure, enabling next-generation AI and HPC workloads with its 3D-stacked photonics engine, *Passage™*. We’re looking for a **Physical Design Flow & Methodology Engineer** to help build the tools, flows, and automation used by our physical design teams to tape out high-performance ASICs and mixed-signal chips. You’ll write production **Python**, use **AI/LLM-based tools** to make flows smarter and faster, and evaluate new EDA capabilities before they reach implementation teams. --- **Responsibilities** - Develop, maintain, and extend physical design flows from synthesis through signoff (P&R, CTS, STA, power integrity, DRC/LVS), mostly in **Python** and **TCL**. - Automate flow tasks using **AI/LLM-based tools** (report triage, debug, constraint checking, DRC/LVS analysis, run monitoring, QoR prediction). - Research and prototype new flow capabilities/methodologies, then transition successful work into production flows. - Build tools for regression testing, QoR tracking, and dashboards to ensure flow changes are measurable and safe. - Support implementation teams by debugging flow problems, reproducing tool issues, and working with EDA vendors on fixes. - Run blocks through the flow to validate methodology changes (timing closure, ECOs, DRC/LVS cleanup). - Write clear documentation and train the PD team on new flows and tools. --- **Qualifications** - Bachelor’s in EE/CE/CS plus **5+ years** related industry experience. - Contributed to at least **one ASIC or mixed-signal chip** through tapeout. - Strong understanding of RTL-to-GDS flow: synthesis, place-and-route, clock tree synthesis, static timing analysis, and physical verification. - Strong **Python** skills (maintainable, tested, version-controlled) and working knowledge of **TCL** and shell scripting. - Practical experience with AI coding assistants/LLMs for automation (or strong interest in learning). - Strong teamwork skills across PD, RTL, verification, CAD, and photonics teams. - Comfortable with ambiguity and changing priorities in a fast-paced research-driven environment. --- **Preferred Qualifications** - Master’s (3+ years) in physical design, or **PhD** in EE/CE/CS. - Hands-on experience with **Cadence** tools (Genus, Innovus, Tempus, Voltus, Pegasus) and/or **Siemens Calibre**. - Experience developing/owning a production PD flow or contributing to CAD/methodology infrastructure. - Familiarity with advanced process nodes (FinFET or newer). - Software engineering practices: **Git**, CI/CD, unit/regression testing, code review. - Experience with **LLM APIs**, agent frameworks, or ML techniques applied to EDA. - Experience with layout data formats/tools (GDS/OASIS, LEF/DEF, KLayout scripting). - Interest in silicon photonics and custom/photonic layout automation. --- **Compensation & Benefits** - **Salary Range:** **$154,000–$175,000 USD** (total compensation includes base salary, new hire equity grant, annual performance-based equity, and other rewards). - Benefits include: comprehensive health care (medical/dental/vision), retirement savings matching, life insurance, generous time off, paid family leave, short/long-term disability, training & development, commuter benefits, flexible hybrid workplace model, and equity grants (full-time employees). --- **Export Control** Candidates should have capacity to comply with federally mandated
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