Principal PCS/PMA RTL Design Engineer
Asteralabs · San Jose, California, United States
About this role
**Astera Labs — Principal PCS/PMA RTL Design Engineer (San Jose, CA)** Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. This role is for a **Principal PCS/PMA RTL Design Engineer** on our **San Jose** design team, focused on **Physical Coding Sublayer (PCS)** and **Physical Medium Attachment (PMA)** logic for high-speed interconnect standards such as **Ethernet, PCIe, UCIe, and UALink**. You will help translate microarchitectural specifications into robust, synthesizable RTL and work cross-functionally with **SerDes/analog, verification, physical design, DFT, firmware, systems, and validation** to deliver designs through **synthesis, timing closure, tapeout, and silicon validation**. --- ## Key Responsibilities ### PCS/PMA RTL design and implementation - Develop synthesizable **Verilog/SystemVerilog RTL** for PCS and PMA digital blocks supporting **Ethernet, PCIe, UCIe, UALink**, and related protocols. - Implement PCS functions including **line encoding/decoding** (64b/66b, 128b/130b, 8b/10b), **scrambling/descrambling**, **block/word alignment**, **lane deskew/reordering**, **gearboxes**, **elastic buffers/FIFOs**, and **rate adaptation**. - Implement **forward error correction** (e.g., **RS-FEC/KP4**, FEC framing, interleaving) plus related **error counters/status logic**. - Implement PMA digital interface logic, including SerDes datapath interfaces (PIPE, SerDes-facing parallel interfaces, UCIe PHY/raw-die interfaces), **CDR control**, **equalization/link training control**, and **calibration/adaptation control**. - Design lane-level and multi-lane logic: **lane bonding**, **polarity/lane reversal**, **PRBS generation/checking**, **loopback modes**, and **BIST** features. - Translate specifications into **datapaths, control logic, state machines, register interfaces, and protocol logic**. - Build reusable, configurable RTL modules supporting multiple protocols, data rates, and lane configurations. - Integrate internal and third-party IP (including analog/mixed-signal PHY macros) following established methodologies. - Participate in design reviews and improve **RTL quality, reuse, latency, performance, power, and area**. ### Verification and design quality - Collaborate with verification engineers on **functional requirements, test plans, and coverage goals** (protocol compliance: **IEEE 802.3, PCI-SIG, UCIe, UALink**). - Debug simulation failures using **waveforms, assertions, regressions, and root-cause analysis**. - Support **lint**, **CDC/RDC**, and RTL quality checks—especially across multi-clock-domain PCS/PMA boundaries and asynchronous lane clocks. - Participate in **UVM-based** verification and help resolve functional/integration issues. - Support **gate-level simulation** and regression debug as needed. ### Synthesis, timing, and implementation - Support **logic synthesis**, constraints development, and implementation flows for high-speed, wide datapaths. - Perform **Static Timing Analysis (STA)** and help resolve setup/hold/clock/interface timing issues (including SerDes/PHY boundaries). - Support **timing closure**, **power optimization**, and **PPA trade-offs** with synthesis/timing/physical design teams. - Assist with **DFT integration**, scan requirements, **low-power intent** (per-lane power states), **ECOs**, and implementation signoff. - Review and debug reports from **Cadence** and/or **Synopsys** digital design flows. ### Silicon and cross-functional collaborat
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