Silicon Design Lead
OpenAI · San Francisco
About this role
## About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. ## About the Role We’re looking for a **Silicon Design Lead** to drive architecture, microarchitecture, and implementation of key IP and subsystems for our AI hardware platforms. You will translate functional, performance, and security requirements into efficient silicon designs—owning technical decisions from architectural definition through implementation and integration. A key part of this role focuses on **hardware security implementation** in close partnership with OpenAI’s Security team. While Security owns the overarching security architecture and requirements, you will translate those requirements into silicon microarchitecture and implementation, balancing security capabilities with performance, power, area, and design complexity. The other part focuses on driving **general silicon architecture/microarchitecture**. ## Responsibilities - Own architecture, microarchitecture, and implementation of silicon IP and subsystems—from requirements and design specifications through integration and validation. - Define hardware interfaces, data flows, and microarchitectural tradeoffs to meet functional, performance, power, and area requirements. - Partner closely with OpenAI’s Security team to translate security architecture, requirements, and threat models into implementable hardware capabilities. - Design and integrate hardware security mechanisms, including encryption, key management, access controls, isolation, and data protection across silicon subsystems. - Evaluate architectural and implementation tradeoffs to ensure security capabilities meet functional and performance requirements. - Collaborate with silicon architects, RTL, verification, firmware, and software teams to drive subsystem design, integration, and validation. - Review and contribute to RTL implementations, ensuring designs align with architectural intent and system requirements. - Evaluate existing and third-party IP, identify architectural or implementation gaps, and drive solutions across subsystem boundaries. ## You Might Thrive If You Have - Strong experience in silicon IP or subsystem-level architecture, microarchitecture, and implementation. - Owned hardware IP or subsystem designs from architectural definition through implementation and integration. - Experience implementing hardware security features such as memory encryption, key management, access controls, isolation, or secure boot. - Ability to translate functional and security requirements into hardware architectures, interfaces, and microarchitectural specifications. - Working knowledge of RTL design and coding proficiency in **Verilog or SystemVerilog** (able to read, review, and contribute to RTL). - Ability to evaluate performance, power, area, and complexity tradeoffs across silicon designs. - Experience working effectively across security, silicon architecture, RTL, verification, firmware, and software teams. - Ideally, broader SoC-level architecture or integration experience (deep IP/subsystem-level expertise is sufficient). ## Additional Notes - **U.S. export control compliance:** Candidates may need to meet certain legal status requirements. - OpenAI is an equal opportuni
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