Emulation Engineer, Hardware Prototyping (HAPS)
Etched · San Jose
About this role
## About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference—backed by hundreds of millions from top-tier investors and staffed by leading engineers. ## What you’ll do - **Own HAPS bring-up**: Take RTL from design teams and get it running on the prototype—covering partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly. - **Expand platform coverage**: Stand up new subsystem configurations so more of the chip is available to software earlier. Each new partition you enable unblocks teams. - **Support your users**: Firmware, driver, and software engineers are your customers. Help them get running, triage failures, and determine whether issues are theirs, the RTL’s, or the platform’s. - **Debug hard problems**: Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and tooling you build yourself. - **Bring up interfaces**: PCIe, Ethernet, HBM and memory models, JTAG, I2C, UART, QSPI—both models and physical bridges. - **Build the flows**: Automate builds, regressions, and image delivery so the platform scales beyond the number of people who understand it. - **Work across the org**: Partner with Design, DV, Silicon Validation, Performance, Firmware, and Software—plus direct collaboration with Synopsys on tool issues and platform capability. ## Representative projects - Bring up a new subsystem partition on HAPS and get firmware booting on it end-to-end. - Build a self-service flow so software users can load and run their own images without prototyping support in the loop. - Instrument deep trace capture across partition boundaries and build tooling to surface it usefully. - Create configurable chip-to-chip and off-chip interface models using prototyping-efficient primitives. - Close timing on a partition that doesn’t want to close, and document the approach so others don’t have to rediscover it. ## You may be a good fit if you have - Hands-on **FPGA prototyping** experience (HAPS, Protium, proFPGA, S2C, or similar), including partitioning, synthesis, timing closure, bring-up, and debug. - Strong **SystemVerilog/Verilog** with practical understanding of what synthesizes well for FPGA. - Solid **C/C++** and **Linux system development**. - Scripting fluency for automation: **Python, TCL, shell**. - Comfort debugging failures you didn’t cause, in code you didn’t write, for users who need an answer today. ## Strong candidates may also have - Experience with **ProtoCompiler**, **Vivado**, or **Synopsys prototyping flows**. - Firmware/driver/bootloader bring-up experience on pre-silicon platforms. - Experience with emulation platforms (ZeBu, Palladium, Veloce) alongside prototyping (we run both; collateral is shared). - **UVM** verification environments, **DFT**, and testbench modeling. - Waveform debug tooling: **Verdi**, **SimVision**. - Cluster/job scheduling experience (**SLURM**), CI systems. ## Benefits - Medical, dental, and vision packages with generous premium coverage - **$500/month credit** for waiving medical benefits - **Housing subsidy: $2,500/month** for those living within walking distance of the office - Relocation support for those moving to **San Jose (Santana Row)** - Wellness benefits (fitness, mental health, and more) - Daily lunch and dinner in our office - Unl
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