MTS, Inference Performance Visibility
Etched · San Jose
About this role
## About Etched Etched is building hardware for frontier intelligence—co-designing chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference, backed by hundreds of millions from top-tier investors. ## Job Summary Join Etched to lead the effort of illuminating the performance landscape of our ML accelerator. You’ll design and build a sophisticated performance analysis tool tailored to our hardware—helping ML engineers and customers understand workload behavior, identify bottlenecks, and unlock the full potential of our systems. ## Key Responsibilities - Lead the design and architecture of a comprehensive performance analysis suite (data collection, processing pipelines, analysis engines, and CLI/GUI interfaces). - Develop robust methods to capture performance data directly from our custom ML accelerator hardware (e.g., hardware performance counters, execution unit status, memory access patterns) via driver interfaces or other mechanisms. - Implement tracing for host-side API calls (runtime libraries, driver interactions) and system-level events (CPU activity, PCIe traffic, memory usage, network contention). - Correlate performance events across host CPU, device driver, PCIe bus, multiple accelerators, and multiple hosts with accurate time synchronization. - Build analysis modules to automatically interpret trace/counter data and identify key performance limiters (compute-bound, memory bandwidth-bound, latency-bound, PCIe-bound, and other hardware bottlenecks). - Create intuitive visualizations (timelines, dependency graphs, resource utilization charts, statistical summaries) to communicate performance characteristics clearly. - Partner with hardware architects, firmware engineers, driver developers, compiler engineers, and ML application engineers to define tool requirements and guide performance analysis/optimization. ## Representative Projects - Architect and implement the core data collection framework for hardware performance counters on a custom PCIe-based accelerator. - Develop a kernel driver module or user-space service for low-overhead tracing of accelerator activity. - Design and build a correlated timeline view (CPU API calls, driver submissions, PCIe transfers, accelerator execution units). - Create an analysis pass to detect and quantify memory access inefficiencies or PCIe bandwidth saturation. ## You Might Be a Good Fit If You Have - Strong proficiency in **C++ or Rust** - **Python** proficiency is a plus - Deep understanding of computer architecture (CPU/accelerators), memory hierarchies (caches/DRAM), and interconnects—especially **PCIe** - Proven experience in low-level performance analysis, profiling, and bottleneck identification on complex hardware systems (GPUs/CPUs/FPGAs/custom accelerators) - Experience with performance analysis tools (e.g., NVIDIA Nsight, AMD uProf, Intel VTune, perf, Tracy, ETW) - Experience working close to hardware (performance counters, device drivers) ## Strong Candidates May Also Have (Nice-to-Have) - Experience developing performance analysis/debugging tools - Experience with ML accelerator architectures (GPUs/TPUs/etc.) - Experience with kernel-mode driver development (Linux or Windows) - Understanding of compiler internals, code generation, and optimization - In-depth knowledge of PCIe protocol and analysis tools (PCIe analyzers) - Experience with multi-chip/
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