Synthesis & STA Engineer – High-Speed SerDes
Asteralabs · San Jose, California, United States
About this role
**Astera Labs — Synthesis & STA Engineer (High-Speed SerDes)** **About Astera Labs** Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. Their Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ technologies with the COSMOS software suite to unify components into cohesive, flexible systems. **Overview** As an **Astera Labs Synthesis & STA Engineer – High-Speed SerDes**, you’ll own the end-to-end flow for **logic synthesis** and **static timing analysis (STA)** across the digital portions of **mixed-signal SerDes PHY designs**. You’ll collaborate closely with analog, RTL, physical design, and verification teams to ensure robust **timing closure at advanced nodes**. **Key Responsibilities** - Perform **RTL synthesis**, optimizing **area, power, and timing** for digital controller and DSP blocks within high-speed SerDes PHY designs. - Author, develop, and validate **SDC constraints** from scratch, including: - clock definitions and **generated clocks** - **multi-frequency / multi-mode** constraints - **I/O delays**, **false paths**, **multicycle paths** - clock-domain crossing exceptions specific to SerDes architectures - Set up and manage **MMMC (Multi-Mode Multi-Corner)** environments for accurate, efficient STA across **PVT corners**. - Drive **timing closure** from synthesis (additional details continue in the source description).
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