Lead RTL Design Engineer
Cerebras · Sunnyvale, CA
About this role
## Lead RTL Design Engineer **About Cerebras** Cerebras Systems builds the world’s largest AI chip—56x larger than GPUs—enabling industry-leading training and inference speeds (over 10x faster than GPU-based hyperscale cloud inference services). Cerebras works with leading model labs, global enterprises, and AI-native startups, including a recent multi-year partnership with OpenAI to deploy 750MW of scale. **About the Role** As a **Lead Front-End RTL Design Engineer**, you’ll be a key part of the world-class team designing and developing the next generations of the **Cerebras Wafer Scale Engine (WSE)**. You’ll bring deep expertise in **RTL design and integration**, with a strong focus on **high performance, power efficiency, and scalability**, and collaborate closely with an **external ASIC vendor**. You’ll work with **design verification, physical design, software, and system teams** to take semiconductor architectures from concept to production—solving the unique challenges of building WSE systems. --- ## Responsibilities - Drive all aspects of chip design, including **Functional Specification, Micro-architecture, RTL development, and Synthesis** - Manage an **external ASIC vendor** through the product development cycle - Partner with **PD** for design closure to meet **PPA goals** - Work with **verification and DFT** teams to achieve strong functional and test coverage - Collaborate with **software and system teams** to deliver optimal performance and features - Debug **silicon-level functional, timing, and power** issues during bring-up --- ## Requirements - **Master’s degree** in Computer Science, Electrical Engineering, or equivalent - Ability to work in a **hybrid** environment - **8–15 years** of experience delivering complex, high-performance, high-quality RTL designs - Experience with **front-end chip integration** and **third-party IP integration** - Demonstrated experience in **networking, HPC, machine learning**, or related fields - Proven track record of **multiple silicon successes** - Experience collaborating with and managing **external vendors** - Experience designing/integrating **high-speed IO** - Networking stack experience including **TCP/IP, RDMA, and Ethernet** - Knowledge of **PCIe, CPU interfaces, and SerDes** - Working knowledge of scripting tools: **Python, TCL** --- ## Assets (Nice to Have) - Experience with **FPGA development toolchains** (Place & Route, Floorplanning, Timing Analysis) --- ## Compensation Base salary range: **$200,000–$299,000** annually. Compensation may include **bonus and equity**, based on experience, skills, and qualifications. --- ## Why Join Cerebras People who are serious about software make their own hardware. Cerebras offers a breakthrough AI platform, opportunities to publish/open-source research, work on one of the fastest AI supercomputers, startup vitality with job stability, and a simple, non-corporate culture. **Apply today** to help drive groundbreaking advancements in AI. *Equal Opportunity Employer.* Privacy: https://www.cerebras.net/privacy/
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