Network Systems Architect
Cerebras · Sunnyvale, CA
About this role
## Network Systems Architect ### About Cerebras Cerebras Systems builds the world’s largest AI chip—56x larger than GPUs—enabling industry-leading training and inference speeds (over 10x faster than GPU-based hyperscale cloud inference). This performance increase is transforming AI application experiences by enabling real-time iteration and additional agentic computation. Cerebras works with leading model labs, global enterprises, and AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras to deploy 750 megawatts of scale: https://openai.com/index/cerebras-partnership/ ### About the Role As a **Network Systems Architect**, you will define **scale-up** (and contribute to **scale-out**) network architecture for current and future Cerebras platforms, including proprietary accelerator interconnects, protocols, and switching. You’ll translate communication patterns and workload behavior into measurable fabric requirements—focusing on **low-latency scale-up** while maintaining enough breadth to define clear boundaries across scale-out and customer-facing networks. Hands-on architectural judgment means your decisions are grounded in prior low-level implementation, modeling, bring-up, or debugging. You will write specifications, guide models and prototypes, make technical decisions, and stay engaged through implementation and qualification. ### Responsibilities - Set the multi-generation architecture and roadmap for Cerebras **scale-up networks** and their interfaces to **scale-out** and **customer-facing networks** - Partner with application, compiler, runtime, and communication-library teams to derive required **bandwidth, latency, ordering, availability, and serviceability** - Define fabric topology, protocols, and switch behavior (routing, buffering, flow control, reliability, fault containment) - Connect data-plane choices to end-to-end system behavior - Decide when to use standards-based technology vs. merchant silicon, and when custom protocol/switch/link/offload is justified - Use performance models, traffic simulation, prototypes, and lab data to test architecture choices and set acceptance criteria - Write architecture and interface specifications, lead design reviews, and drive cross-layer decisions through implementation, bring-up, and qualification ### Qualifications - BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent practical experience) - Typically **12+ years** of relevant industry experience, including principal-level technical ownership of a major networking/switching/accelerator/HPC system from architecture through implementation or deployment - Deep expertise in low-latency or proprietary interconnects, fabric protocols, switch architecture, or closely related areas (including data-plane depth for switch pipelines, buffering, routing, flow/congestion control, and reliability) - Experience deriving network requirements from incomplete workload/system information, with the ability to make decisions across software, accelerator I/O, topology, and physical constraints - Working knowledge of **Ethernet, IP, and RDMA**; conceptual familiarity with **BGP and EVPN** and tradeoffs between routed networks and simpler low-latency scale-up designs - Architectural judgment grounded in prior implementation, modeling, silicon, lab, bring-up, or debugging - Proven record of making clear technical decisions and influencing engineering leaders
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