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Datacenter & Agentic AI Workload Performance Analysis Engineer

Tenstorrent · Santa Clara, California, United States

remoteunknown$100,000–$500,000Posted Oct 1, 2026C/C++PythonBash/ShellLinux perfQEMUstraceRISC-VCPU microarchitecture simulators

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About this role

**Tenstorrent — Datacenter & Agentic AI Workload Performance Analysis Engineer** Tenstorrent is leading the industry on cutting-edge AI technology—revolutionizing performance expectations, ease of use, and cost efficiency. We’re growing our team and looking for contributors of all seniorities. In this role, you’ll help shape the performance of next-generation **RISC-V CPUs** across modern **datacenter and agentic AI workloads**. You’ll work at the intersection of **hardware and software**, bringing real-world applications onto RISC-V platforms, characterizing behavior, and using workload analysis to uncover opportunities for better **CPU performance, efficiency, and scalability**. You’ll collaborate closely with **CPU architects, RTL designers, software engineers, and compiler teams** to understand how demanding workloads exercise the CPU and translate those insights into architectural improvements—ranging from reducing large production workloads for performance modeling to correlating simulation results with hardware behavior. **Remote (North America)** We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level. --- ## Who You Are - Strong background in **CPU performance analysis**, **workload characterization**, or **computer architecture**, with experience connecting software behavior to hardware performance. - Understanding of modern CPU microarchitecture: **superscalar pipelines**, **speculative execution**, **memory hierarchies**, and **vector/SIMD** architectures. - Enjoys digging into complex workloads using **profiling and simulation data** to identify bottlenecks and turn analysis into actionable recommendations. - Comfortable working across hardware and software—from **CPU microarchitecture and RTL** to **operating systems, compilers, runtimes, and applications**. - Strong technical communicator who enjoys collaborating with architects, designers, and software engineers. ## What We Need - **PhD** in Computer Engineering, Electrical Engineering, Computer Science, or related field, with strong research or industry experience in workload characterization, benchmark development, performance analysis, or simulation. - Deep understanding of **CPU architecture and RISC-V**, including pipelines, speculative execution, vector/SIMD extensions, memory hierarchies, and performance tradeoffs. - Hands-on experience with performance analysis and simulation tools such as **Linux perf**, **strace**, **QEMU**, or CPU microarchitecture simulators. - Strong programming skills in **C/C++**, **Python**, **Bash/Shell**, and assembly or intrinsic programming; experience working close to the hardware/software boundary. - Strong understanding of systems software: **operating systems**, **virtualization**, **compilers**, **runtimes**, and **GNU/RISC-V software ecosystems**. ## What You Will Learn - How real-world datacenter and agentic AI workloads influence CPU microarchitecture and architectural decisions. - How to connect workload characterization and performance modeling to CPU design, **RTL implementation**, emulation, and silicon. - How hardware/software co-design can improve **throughput**, **scalability**, and **performance-per-watt**. - How to analyze complex production workloads and reduce them into representative workloads and traces for architectural exploration. - How emerging RISC-V capabilities, cloud infrastructur

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