Digital RTL Design Engineer- Static Timing Analysis
Asteralabs · San Jose, California, United States
About this role
## Astera Labs — Digital RTL Design Engineer (Static Timing Analysis) ### Role overview Astera Labs is seeking a **Digital RTL Design Engineer – Static Timing Analysis** to join our **San Jose** design team. In this role, you will contribute to the **architecture, implementation, integration, and verification** of digital logic for **high-performance connectivity and networking ASICs**. You will translate microarchitectural specifications into **robust, synthesizable RTL**, and collaborate closely with **verification, physical design, DFT, firmware, systems, and validation** teams to deliver reliable designs through **synthesis, timing closure, tapeout, and silicon validation**. ### Key responsibilities **RTL design and implementation** - Develop synthesizable **Verilog/SystemVerilog RTL** for digital ASIC blocks and subsystems - Translate specifications into **datapaths, control logic, state machines, register interfaces, and protocol logic** - Build **reusable, configurable RTL modules** for high-performance connectivity products - Integrate internal and third-party IP following established coding/design methodologies - Participate in design reviews and improve **RTL quality, reuse, performance, power, and area** **Verification and design quality** - Collaborate with verification engineers on **functional requirements, test plans, and coverage goals** - Debug simulation failures using **waveforms, assertions, regressions, and root-cause analysis** - Support **lint**, **CDC/RDC**, and RTL quality checks - Participate in **UVM-based** verification and help resolve functional/integration issues - Support **gate-level simulation** and regression debug as needed **Synthesis, timing, and implementation** - Support **logic synthesis**, constraints development, and implementation flows - Perform **STA (Static Timing Analysis)** and help resolve **setup/hold/clock/interface timing** issues - Support **timing closure**, **power optimization**, and **PPA trade-offs** with synthesis/timing/physical-design teams - Assist with **DFT integration**, scan requirements, low-power intent, **ECOs**, and implementation signoff - Review and debug reports from **Cadence and/or Synopsys** digital design flows **Silicon and cross-functional collaboration** - Support block/subsystem integration through **tapeout milestones** - Collaborate with **physical design, DFT, firmware, systems, packaging, and validation** teams - Participate in **silicon bring-up**, post-silicon debug, and failure analysis - Document design decisions, issues, and technical solutions clearly for cross-functional stakeholders ### Basic qualifications** - Bachelor’s degree in **Electrical Engineering, Computer Engineering, or related field** - **Master’s degree preferred** - **3+ years** relevant experience in **digital ASIC/SoC/FPGA-to-ASIC/RTL** (or equivalent) - Hands-on experience with **Verilog/SystemVerilog RTL development** - Understanding of digital design fundamentals: **combinational/sequential logic, clocks/resets, state machines, datapaths, FIFOs, interfaces** - Experience with **RTL simulation, debugging, synthesis, and basic timing analysis** - Familiarity with ASIC design flows and cross-team collaboration - Strong communication skills in a collaborative, fast-paced environment - Ability/willingness to work **onsite in San Jose, CA** ### Preferred qualifications** - Experience with **PCIe, Ethernet, NVMe, CXL, UALink, AMBA**, or other high-speed interface protocols
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