Sr. Staff Engineer, Front-End Verification
Tenstorrent · Austin, Texas, United States; Santa Clara, California, United States
About this role
**Sr. Staff Engineer, Front-End Verification** **About Tenstorrent** Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. We've developed a high-performance RISC-V CPU from scratch and are building the best AI platform possible. **The Role** We're looking for a Design Verification Engineer to contribute to unit-level verification of our RISC-V CPU front-end, including instruction fetch, branch prediction, and fetch control structures. You'll build testbenches, generate stimulus, and develop checkers for complex microarchitectural scenarios. **Location:** Hybrid (Austin, TX or Santa Clara, CA) **Who You Are** • **Front-End Experience:** Solid background verifying CPU front-end blocks (instruction fetch, branch predictors, instruction caches/TLBs, decode) using SystemVerilog, UVM, and C++ • **Unit-Level Focus:** Hands-on experience building clean, controllable unit testbench environments • **Reusable Design:** Pragmatic approach to building transactors, predictors, and scoreboards • **Collaborative Problem Solver:** Comfortable working with RTL designers on fetch bugs and edge cases **What You'll Do** • Build and maintain UVM testbenches for instruction fetch units and branch predictors • Develop constrained-random and directed tests for speculation, misprediction flows, and cache interactions • Develop and maintain C++ reference models and predictors • Execute verification plans and track coverage metrics **What You'll Learn** • RISC-V front-end microarchitecture and high-performance fetch pipelines • Strategies for maintainable DV infrastructure • Industry-standard and open-source simulation tools (Verilator, etc.) • Cross-team collaboration with RTL, performance, and software teams **Compensation** $100k - $500k including base and variable compensation (based on experience, skills, education, background, and location) *Equal opportunity employer. Employment contingent on eligibility to access U.S. export-controlled technology.*
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